Conventional analog circuits frequently include high-voltage (HV) devices such as drain extended metal oxide semiconductor (DEMOS) transistors and buried collector bipolar transistors. Such analog circuits can operate at supply voltages of above 100 volts. It is desirable to integrate the HV devices with complementary metal oxide semiconductor (CMOS) devices on the same integrated circuit (IC) chip using a single process to reduce cost and complexity. In one arrangement an island (e.g., silicon island) having low voltage CMOS devices that can be an electrostatic discharge (ESD) sensitive region of the IC is surrounded by a HV “tank” having high voltage devices, and is thus embedded within. The island is junction isolated from the HV tank and they may be in proximity to one another.
The devices in the island and the devices in the HV tank both generally include a buried layer thereunder. The layout design rule for ESD tolerance of a given IC can specify a maximum spacing between the buried layer in the island to buried layer in the HV tank, where the breakdown voltage from devices at the edge of the island to the HV tank generally decreases as this spacing decreases.